This invention relates to an xcex1(alpha)-ray assurance technology in semiconductor devices. More particularly, this invention relates to a technology for preventing an error operation of flip-flop circuits due to the xcex1-rays, and provides flip-flop circuits having high xcex1-ray resistance, a semiconductor device, a designing method of the semiconductor device and a database for the designing method.
A flip-flop type latch circuit has widely been employed as a circuit for temporarily holding data or a signal level in semiconductor integrated circuits, particularly in logical integrated circuits.
As an amount of the charge built up inside a flip-flop circuit becomes smaller with microstructuring of semiconductor elements in a semiconductor integrated circuit, inversion of a potential due to the charge generated by the xcex1-rays is more likely to develop. The semiconductor integrated circuit uses a large number of flip-flop circuits, in particular. Since the number of constituent elements is large, too, the flip-flop circuit is constituted in most cases by the smallest constituent devices. Once the potential is inverted, it continues outputting error values until a normal value is acquired next, and the influences are great, too. For this reason, the error operation resulting from the xcex1-rays is more likely to occur. To cope with the xcex1-rays, proposals have been made in the past to positively apply a capacitor to internal nodes of the flip-flop circuit or to intentionally increase parasitic capacitance (refer to JP-A-10-199996).
In the semiconductor integrated circuit, the size of the semiconductor element (hereinafter also called merely the xe2x80x9celementxe2x80x9d) and the operation frequency are substantially inversely proportional to each other. Therefore, to suppress the increase of power consumption due to the increase of the operation frequency, the flip-flop circuit is designed in many cases in such a fashion that parasitic capacitance of internal nodes decreases in proportion to miniaturization of the semiconductor elements. On the other hand, the amount of the charge that is generated when the xcex1-rays pass through the flip-clop circuit decreases with miniaturization of the elements, but the amount of its decrement is smaller than the amount of decrease of the parasitic capacitance of the internal nodes brought forth by miniaturization of the element.
It has been found that the xcex1-ray assurance technology that applies the capacitance to the internal node involves the following problems. As miniaturization of the devices proceeds, a capacitor of a relatively greater capacitance becomes necessary inside the flip-flop circuit, and the operation speed, power consumption and an occupying area are sacrificed. Whenever the size of devices constituting the flip-flop circuit or the value of a power source voltage used is changed, the capacitance to be imparted to the internal nodes of the flip-flop circuit must be estimated once again and this becomes a large burden to design.
MOS transistors having a high threshold value are often used to constitute a logic circuit in CMOS-LSI to reduce a standby current. When the threshold value of the MOS transistors is raised, however, driving power drops and ON resistance becomes great. Consequently, it becomes more difficult for the node, whose potential has changed due to the xcex1-rays, to return to the original potential. In this case, a logic gate of a next stage is more likely to respond to the change before the return of the potential and to cause an error operation. The power source voltage of LSI has been lowered, but the error operation becomes more likely to occur when the power source voltage drops and driving power of the MOS transistors drops, or when the amount of the charge built up in the internal node decreases.
It is an object of the present invention to provide a semiconductor integrated circuit technology that can ensure xcex1-ray resistance or xcex1-ray immunity of flip-flop circuits even when semiconductor elements are miniaturized.
It is another object of the present invention to provide a semiconductor integrated circuit technology that does not require to design once again a circuit construction of flip-flop circuits or capacitance of internal nodes in accordance with the size of semiconductor elements or with a value of a power source voltage to ensure xcex1-ray resistance of the flip-flop circuits even when the semiconductor elements are miniaturized or when the value of the power source voltage is changed.
It is still another object of the present invention to provide a semiconductor integrated circuit technology that can prevent the error operation resulting from the xcex1-rays of flop-flop circuits even when a threshold value of MOS transistors is raised or when the value of the power source voltage used becomes lower.
These and other objects and novel features and advantages of the present invention will become more apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.
Typical aspects of the present invention disclosed herein are as follows.
According to an aspect of the present invention, a data hold circuit comprises at least three flip-flop circuits for inputting the same signal, and a majority logic circuit for outputting a signal in accordance with a logic value of the majority of the outputs of the flip-flop circuits. Therefore, even when an xcex1-ray passes through any of the flip-flop circuits and the output changes, the other flip-flop circuits can keep a correct output signal and reliability of the circuit can be improved. Moreover, unlike a flip-flop circuit that is so constituted as to keep a level by means of only the charge of capacitor, the data hold circuit of this invention can reliably avoid the error operation resulting from the xcex1-ray even when the elements are miniaturized.
In the aspect of the present invention described above, the three or more flip-flop circuits described above are so constituted as to acquire input signals on the basis of mutually different clock signals synchronized with one another. In consequence, the data hold circuit can keep a correct output signal even when any noise overlaps with the clock signals or when an error pulse occurs due to the incidence of the xcex1-rays to clock amplifiers and any of the flip-flop circuits acquire an error data, and reliability of the circuit can be further improved.
In the construction described above, two flip-flops among the three flip-flop circuits acquire the input signals on the basis of mutually different two clock signals synchronized with each other, and the other one flip-flop circuit is so constituted as to use the two clock signals as its input and to acquire its input signal on the basis of an output signal of a logic circuit whose output changes in accordance with the normal change of these clock signals. This construction can prevent the error operation of the flip-flop circuits due to the noise overlapping with the clock signals and due to the incidence of the xcex1-rays to the clock amplifier, and can decrease the number of signal lines for supplying the clock signals. The clock signal for the flip-flop circuits may be used in common, provided that the influences of the noise and the xcex1-rays on the clock signals can be neglected.
The flip-flop circuit described above is a flip-flop circuit with a diagnosis function that is equipped with a scan-in terminal and a scan-out terminal for test data. Therefore, it is possible to diagnose each of the majority logic circuit and the flip-flop circuit.
In two of the three flip-flop circuits described above, switch means for switching common scan-in data and the output from the scan-out terminal of the other flip-flop circuit is disposed as a pre-stage circuit of the scan-in terminal. When the common scan-in data is selected, the number of scan-in data can be decreased and a general logic circuit among the flip-flops can be efficiently diagnosed. When the scan-out terminal of the other flip-flop circuit is selected, the number of scan-in data increases, but the diagnosis of the majority logic circuit and the flip-flop circuits becomes possible, and when these two test modes are switched and selected, the test of the overall circuit can be made efficiently.
According to another aspect of the present invention, a data hold circuit comprises two flip-flop circuits so constituted as to input the same signal and to acquire an input signal on the basis of the same clock signal or mutually different clock signals synchronized with each other, and a logic circuit whose output changes in accordance with the normal change of output signals of the flip-flop circuits. Consequently, even when the xcex1-rays pass through any of the flip-flop circuits and change its output, the output of the logic circuit of the subsequent stage does not change so long as both outputs change. Therefore, the correct output signal can be kept and reliability of the circuit can be improved. Unlike the flip-flop circuit so constituted as to suppress the inversion of the level by means of the charge of the capacitance upon incidence of the xcex1-rays, the data hold circuit of this invention can reliably avoid the error operation resulting from the xcex1-rays even when the devices are miniaturized.
Here, it is possible to use, as the logic circuit described above, a circuit which has first and second inputs and one output, and in which the logic value of the output is equal to the input when the logic values of the first and second input are equal to each other, and is equal to the logic value of a just previous output when the logic values of the first and second inputs are different from each other, or a circuit which has first and second inputs and one output, and in which the logic value of the output is an inversion value of the input when the logic values of the first and second inputs are equal to each other, and is equal to the logic value of the just immediate output when the logic values of the first and second inputs are different from each other, or a circuit which has first and second inputs and one output, and in which the logic value of the output is equal to the logic value of the just previous output when the logic values of the first and second inputs are equal to each other, and is equal to the logic value of the first input when the logic values of the first and second inputs are different from each other.
The logic circuit described above can be constituted in the following way, too. The logic circuit comprises a majority logic circuit which has three inputs and one output and the output of which is decided by the majority of at least two inputs. The three inputs are the outputs of the two flip-flop circuits described above and the output of the majority logic circuit. In this way, a logic circuit operating statically can be accomplished, and correct data can be held even when the flip-flop circuits do not operate for a long time.
Further, the logic circuit includes first and second differential circuits each receiving the clock signal described above supplied as a differential signal, and outputting a signal that changes in accordance with the change of the clock signal, wherein the two flip-flop circuits described above are so constituted as to acquire the inputs, respectively, on the basis of the outputs of the first and second differential circuits. In consequence, even when the noise having the same phase overlaps with the clock signal, it becomes possible to prevent the flip-flop circuits from erroneously fetching the data.
The first and second differential circuits are constituted in such a fashion that their outputs are equal to the logic value of either one of the clock signals when the logic values of the differential clock signals inputted are different from each other, and are equal to the logic value of the just immediate output when the logic values of the differential clock signals are equal to each other. In this way, it is possible to prevent the flip-flop circuits from erroneously fetching the data even when the noise overlaps with either one of the differential clock signals or when the xcex1-rays are incident to the clock amplifiers.
Further, the flip-flop circuit described above uses a flip-flop circuit with a diagnosis function that is equipped with a scan-in terminal and a scan-out terminal for test data. Therefore, each of the logic circuit and the flip-flop circuit can be diagnosed.
A data hold circuit according to still another aspect of the present invention comprises first and second flip-flop circuits using the same signal as an input, and acquiring input signals on the basis of the same clock signal or mutually different clock signals synchronized with each other, first and second logic circuits whose output changes in accordance with the normal change of the output signals of the flip-flop circuits, a third flip-flop circuit using the output signal of the first logic circuit as an input thereof, a fourth flip-flop circuit using the output signal of the second logic circuit as an input thereof, and a third logic circuit whose output changes in accordance with the normal change of the output signals of the third and fourth flip-flop circuits, wherein the first and second flip-flop circuits enter a data-through state in the first state of the clock signal and a data-hold state in the second state of the clock signal, and the third and fourth flip-flop circuits enter the data-hold state in the first state of the clock signal and the data-through state in the second state of the clock signal. Accordingly, even when the xcex1-rays pass through the flip-flop circuit simultaneously with the change of the clock signal and the error operation in which the output that should inherently change does not change occurs, the data hold circuit can hold the correct data.
A semiconductor device according to still another aspect of the present invention comprises an internal circuit having the data hold circuit described above and constituted by MOS transistors, and an output circuit for receiving signals from the internal circuit and outputting signals to outside, wherein a gate width of the MOS transistors constituting the data hold circuit is smaller than at least a gate width of MOS transistors constituting the output circuit. Therefore, even when the device size of the MOS transistors constituting the flip-flop circuits are small, too, the error operation of the flip-flop circuits resulting from the xcex1-rays can be reliably avoided.
In the semiconductor device having bonding bumps at a center portion of a semiconductor chip on which the semiconductor device including a data hold circuit is formed, the data hold circuit disposed in the proximity of the bumps includes a plurality of flip-flops for inputting the same signal, and has a multiplex structure whose output changes in accordance with a logic value of the majority of the outputs of the flip-flops. Therefore, even when the material of the bumps itself emits the xcex1-rays, the flip-flops in the proximity of the bumps have high xcex1-ray resistance, and a circuit in which the error operation due to the xcex1-rays is difficult to occur can be obtained.
According to still another aspect of the present invention, there is provided a method of designing a semiconductor device including flip-flop circuits by utilizing a computer, comprising the steps of inputting an allowable error operation number per predetermined time into the computer, and selecting a circuit to be used from among those circuits which are registered in advance, on the basis of the allowable error operation number per predetermined time so inputted. Thereby, it becomes possible to use a circuit highly resistant to the xcex1-rays for a circuit having a small allowable error operation number per predetermined time and a circuit having low resistance to the xcex1-rays but having a small number of devices for a circuit having a large number of allowable error operation umber per predetermined time. In this way, the error operation resulting from the xcex1-rays can be reduced while the increase of an occupying area of circuits is restricted.
Preferably, the step of selecting the circuit selects a circuit to be used from the circuits registered in advance, on the basis of the allowable error operation number per predetermined time so inputted and a required speed. Thereby, a semiconductor device having less error operation resulting from the xcex1-rays and capable of operating at a desired speed can be accomplished.
The step of selecting the circuit described above selects the circuit to be used in accordance with the degree of the allowable error operation number per predetermined time inputted from at least two circuits consisting of a multiplex data hold circuit using a plurality of flip-flop circuits and a majority logic circuit, a duplex data hold circuit using two flip-flop circuits and a logic circuit for eliminating an error pulse, a data hold circuit equipped with capacitor that positively applies the capacitor to internal nodes, and a high multiplying type data hold circuit that improves driving force by connecting a plurality of inverters in parallel, when it selects the data hold circuit. In this way, the error operation resulting from the xcex1-rays can be reduced while the increase of the occupying area is restricted.
The step of selecting the circuit described above selects the circuit to be used from at least two consisting of a multiplex data hold circuit using a plurality of flip-flop circuits and a majority logic circuit, a duplex data hold circuit using two flip-flop circuits and a logic circuit for eliminating an error pulse, a data hold circuit equipped with capacitor that positively applies the capacitor to internal nodes, and a high multiplying type data hold circuit that improves driving force by connecting a plurality of inverters in parallel, in accordance with the degree of the allowable error operation number per predetermined time inputted, a package structure employed, a process, a wiring material and an arrangement of bumps. Thereby, the error operation resulting from the xcex1-rays can be reduced while the increase of the occupying area is restricted, and a semiconductor device having high reliability and capable of preventing reliably the error operation resulting from the xcex1-rays irrespective of the package structure, the process, the wiring material and the bump arrangement can be accomplished.
According to still another aspect of the present invention, there is provided a database registering a plurality of unit circuit information having the same function, for use in a designing method of a semiconductor device by utilizing a computer, wherein the unit circuit information contains information about an allowable error operation umber per predetermined time. Therefore, a semiconductor device can be accomplished that comprises an optimum combination of circuits in accordance with the allowable error operation number per predetermined time required for the circuits.
Preferably, the database described above further includes unit circuit information having information about the allowable error operation number and unit circuit information not having information about the allowable error operation number. According to this arrangement, the information about the allowable error operation number need not be prepared for all the unit circuits, and configuration of the database becomes easier.